1. Field of the Invention
The present invention relates to a method for manufacturing a single crystal semiconductor layer. In addition, the present invention relates to a method for manufacturing a semiconductor substrate including a single crystal semiconductor film and a method for reprocessing a semiconductor substrate.
2. Description of the Related Art
Integrated circuits using an SOI substrate where a thin single crystal semiconductor layer is formed on an insulating surface, instead of a bulk silicon wafer, have been developed. The use of an SOI substrate can reduce parasitic capacitance between a drain of a transistor and a substrate; thus, SOI substrates are attracting attention for their ability to improve performance of semiconductor integrated circuits.
A Smart Cut method is known as one of methods for manufacturing an SOI substrate (e.g., see Patent Document 1). An outline method for manufacturing an SOI substrate by a Smart Cut method is described below. Hydrogen ions are implanted into a silicon wafer to form a microbubble layer at a predetermined depth from the surface. The silicon wafer into which hydrogen ions have been implanted is bonded to another silicon wafer with a silicon oxide film interposed therebetween. After that, by performing heat treatment, the microbubble layer is to be a cleavage plane, and the wafer into which the hydrogen ions are implanted is peeled in a thin film state. A Smart Cut method is also called a “hydrogen ion implantation separation method”.
In Patent Document 1, in order to improve the planarity of the surface of the single crystal silicon layer and repair a defect in the single crystal silicon layer, CMP treatment and/or heat treatment at high temperature (about 1200° C. or lower) is performed after the single crystal silicon layer is formed.
Further, a method for reusing the silicon wafer after a single crystal silicon layer is peeled off and transferred from a silicon wafer by a Smart Cut method is known (e.g., see Patent Document 2). In Patent Document 2, after the single crystal silicon layer is peeled off from the silicon wafer, the silicon wafer is planarized by CMP treatment or the like.
[References]
[Patent Documents]
    [Patent Document 1] Japanese Published Patent Application No. 2003-017671    [Patent Document 2] Japanese Published Patent Application No. H11-097379